The present invention relates to an amplifier circuit of high precision type having a sample-and-hold function, relates to pipelined A/D (analog-to-digital) and D/A (digital-to-analog) converters respectively using such an amplifier circuit of high precision type, and particularly relates to the circuits and converters realizing low power consumption and high operational speed.
Conventionlly, when realizing an amplifier circuit of high precision type having a sample-and-hold function (hereinafter referred to as SHA circuit), it was necessary to use an operational amplifier having a high DC gain. According to the operational amplifier having such a high DC gain, a plurality of operational amplifiers are connected with each other in a series manner. For example, IEEE Symposium on VLSI Circuits, pages 94 to 95, published in 1996, discloses an SHA circuit in which two operational amplifier stage are used and a pipelined A/D converter using such an SHA circuit. The following description deals with the operational principle of the SHA circuit with reference to FIG. 13.
The SHA circuit shown in FIG. 13 is provided with an operational amplifier 100, capacitors 106p and 106m that carry out the samplings of respective input signals from voltages VINP and VINM, capacitors 107p and 107m via which respective negative feedback are formed in the operational amplifier 100, phase compensation capacitors 104p and 104m, and a plurality of switches 103, 105p, 108p, 109p, 105m, 108m, and 109m which are respectively realized by an analog switch. The operational amplifier 100 is realized by first and second operational amplifier stages 101 and 102 that are connected with each other in a series manner so as to respectively carry out the sample-and-hold operation, the amplification, and addition and subtraction operations with respect to the analog signal with high precision. The phase compensation capacitors 104p and 104m compensate the deterioration of phase margin occurred when the first and second operational amplifier stages 101 and 102 are connected with each other in a series manner.
According to the SHA circuit having the above circuit configuration, in a sampling phase xcfx86s during which the input signal is subjected to the sampling, (a) two pairs of input-output terminals of the first operational amplifier stage 101 are connected with each other (short-circuited) via the switches 105p and 105m, respectively and (b) two output terminals of the second operational amplifier stage 102 are connected with each other (short-circuited) via the switch 103. The switch 108p is operated so that the voltage VINP is applied to an electrode of the capacitor 106p. The switch 109p is operated so that a reference voltage VREF is applied to an electrode of the capacitor 107p which is provided on the upper stream side of the feedback during the negative feedback. The switch 108m is operated so that the voltage VINM is applied to an electrode of the capacitor 106m on the input terminal side. The switch 109m is operated so that the reference voltage VREF is applied to an electrode of the capacitor 107m which is provided on the upper stream side of the feedback during the negative feedback. This allows that the capacitor 106p carries out the sampling of one input signal from the voltage VINP, the capacitor 106m carries out the sampling of another input signal from the voltage VINM, and the capacitors 107p and 107m carry out the sampling of the difference between the reference voltage VREF and an offset voltage (1/f noise) of the first operational amplifier stage 101, respectively.
In general, the gate area of an input transistor in the second operational amplifier stage 102 is several times to several tens times as large as that of the first operational amplifier stage 101. This causes the offset voltage and the 1/f noise to be smaller in the second operational amplifier stage 102 than in the first operational amplifier stage 101. The offset voltage and the 1/f noise of the second operational amplifier stage 102 that are viewed from the input terminals of the first operational amplifier stage 101 are equal to the division of the offset voltage of the second operational amplifier stage 102 by the DC gain A1 of the first operational amplifier stage 101. Accordingly, in most cases, the offset voltage and the 1/f noise are negligible.
In the next hold phase xcfx86h, (a) the two pairs of input and output terminals of the first operational amplifier stage 101 are cut off by the switches 105p and 105m, respectively and (b) the two output terminals of the second operational amplifier stage 102 are also cut off by the switch 103. The switch 108p is operated so that the reference voltage VREF is applied to the capacitor 106p. The switch 109p is operated so that a voltage VOUTP which is one output of the second operational amplifier stage 102 is applied to the electrode of the capacitor 107p which is provided on the upper stream side of the negative feedback. The switch 108m is operated so that the reference voltage VREF is applied to the electrode of the capacitor 106m on the input terminal side. The switch 109m is operated so that a voltage VOUTM which is another output of the second operational amplifier stage 102 is applied to the electrode of the capacitor 107m which is provided on the upper stream side of the negative feedback. In the sampling phase xcfx86s, the calculation is carried out in accordance with the conservation law of electric charges between the electric charges charged by the capacitor 106p and the electric charges charged by the capacitor 107p. Also, the calculation is carried out in accordance with the conservation law of electric charges between the electric charges charged by the capacitor 106m and the electric charges charged by the capacitor 107m. The calculations allow to output a voltage (VOUTPxe2x88x92VOUTM) that is the difference between the two output terminals of the second operational amplifier stage 102.
FIG. 14 is a block diagram showing a circuit configuration of a conventional pipelined A/D converter. In the pipelined A/D converter, a sample-and-hold circuit 111 that holds voltages VINP and VINM of the input signal, and a plurality of sub-stages STG11, STG12, STG13, and STG14 are connected with each other in this order in a series manner. Each of the sub-stages is connected with a digital error correction circuit (logic) 119. The sub-stage STG11 is composed of a sub-D/A converter 112 and a sub-A/D converter 113. The sub-stage STG12 is composed of a sub-D/A converter 114 and a sub-A/D converter 115. The sub-stage STG13 is composed of a sub-D/A converter 116 and a sub-A/D converter 117. The sub-stage STG14 is composed of only a sub-A/D converter 118.
The sample-and-hold circuit 111, and the sub stages STG12 and STG14 are operated in response to a clock signal CLK. The sub-stages STG11 and STG13 are operated in response to an inverted signal that is a resultant of inversion of the clock signal CLK by an inverter 120. Namely, an even-numbered sub-stage and an odd-numbered sub-stage are operated in accordance with respective timings so as to have a phase difference of 180xc2x0. Each sub-A/D converter carries out the A/D conversion of the input signal of the sub-stage to which the sub-A/D converter belongs so as to determine a predetermined-numbered bit (the n-th bit (n: a predetermined number)) which is outputted to the sub-D/A converter of its sub-stage and the digital error correction circuit 119. Each sub-D/A converter determines an output voltage in accordance with the difference between an analog input signal voltage of the sub-stage and an analog voltage corresponding to the bit information that has been outputted from the sub-A/D converter, and the output voltage is outputted to the next sub-stage. Thus, each bit of the digital output is successively determined by the sub-stages STG11 through STG14, the error correction is carried out by the digital error correction circuit 119 so as to output a 4-bit digital signal.
FIG. 15 shows an example of the circuit configuration of the respective D/A converters. Each sub-D/A converter shown in FIG. 14 has a differential structure. However, for brevity, FIG. 15 shows a single ended circuit configuration. The sub-D/A converter shown in FIG. 15 has basically the same circuit configuration in which the SHA circuit shown in FIG. 13 is realized by a single ended circuit configuration. More specifically, operational amplifier stages 121 and 122 correspond to the operational amplifier stages 101 and 102, respectively. Capacitors 126 and 127 correspond to the capacitors 106p and 107p, respectively. A phase compensation capacitor 124 corresponds to the phase compensation capacitor 104p. Switches 125, 128, and 129 correspond to the switches 105p, 108p, and 109p, respectively.
In order to realize a 1-bit D/A converter, a switch 130 is connected with the terminal on the xcfx86h side of the switch 128 that should be made contacted during the hold phase xcfx86h so as to switch between the reference voltages +VREF and xe2x88x92VREF in accordance with the bit information from the sub-A/D converter. One of the terminals of the switch 129 is connected with the input terminal of the sub-D/A converter. Further provided is a switch 131 that cuts off an output terminal of the operational amplifier stage 122 from a ground voltage (GND voltage) during the hold phase xcfx86h. An output voltage of the operational amplifier stage 121 is applied to the operational amplifier stage 122 via an inverting amplifier stage 123 whose gain is equal to xe2x88x921. Each one input terminal of the operational amplifier stages 121 and 122 is connected with the GND voltage.
According to the SHA circuit shown in FIG. 13, the operational amplifier stage 101 carries out the offset compensation during the sampling phase xcfx86s. However, the operational amplifier stage 102 of the next stage always consumes the power although it does not directly affect the operational proceeding. The power consumption of the operational amplifier stage 102 is more than several times of that of the operational amplifier stage 101. This causes the above power consumption to occupy most part of the power consumption of the SHA circuit.
The present invention is made in view of the foregoing problem, and its object is to provide a sample-and-hold amplifier circuit that can realize the low power consumption, and to provide pipelined A/D converter and pipelined D/A converter respectively using such a sample-and-hold amplifier circuit. In addition to the above object, it is another object of the present invention to make operate at a high speed each of the sample-and-hold amplifier circuit, the pipelined A/D converter, and the pipelined D/A converter.
In order to achieve the object, a sample-and-hold amplifier circuit in accordance with the present invention is provided with a sampling circuit that carries out the sampling of an input signal and an operational amplifier that carries out the operational amplification of the input signal that has been subjected to the sampling by the sampling circuit. The operational amplifier is further provided with first and second operational amplifier stages that are connected with each other in a series manner, a switch, provided between an output terminal of the first operational amplifier stage and an input terminal of the second operational amplifier stage, that connects or cuts off the connection of the first and second operational amplifier stages so as to be nonconductive in a first operation phase during which the sampling is carried out and so as to be conductive in a second operation phase during which the operational amplifier entirely carries out the operational amplification, and a phase compensation capacitor provided between an output terminal and the input terminal of the second operational amplifier stage.
With the arrangement, since the switch becomes nonconductive in the first operation phase, the output voltage of the second operational amplifier stage is not reset during the sampling. This allows that, during the first operation phase, the second operational amplifier stage carries out, together with the phase compensation capacitor, the holding operation of the voltage that has been subjected to the operational amplification in the second operation phase during which the switch is conductive (closed).
Thus, it is possible to use the power consumption of the second operational amplifier stage for the signal processing, in the first operation phase. Accordingly, it is possible to prolong the period of time during which the output signal is outputted from the sample-and-hold amplifier circuit. This is based on the fact that, when the sample-and-hold amplifier circuit is operated in response to the operation clock having a duty ratio of 50 percent, the period of time during which the output signal is outputted from the second operational amplifier stage becomes doubled compared with the conventional case. This indicates that it is possible to prolong the period of time for sending the signal that has been amplified by the sample-and-hold amplifier circuit to the next stage. Since the load is driven for a longer time, the low power consumption can be realized, accordingly. Further, it is possible to use the power consumption of the second operational amplifier stage for the signal processing, in the first operation phase. This causes the output voltage of the sample-and-hold amplifier circuit to vary a little when the frequency of the input signal is low. This allows to alleviate a slewing rate of the second operational amplifier stage and to realize the low power consumption.
As has been described above, it is possible to provide a sample-and-hold amplifier circuit that can realize the low power consumption.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus, are not limitative of the present invention.